Phase-locked loop frequency synthesizer including controllable synchronous frequency dividers controlled by a common frequency dividing control signal

摘要

A phase-locked loop frequency synthesizer includes a first variable frequency divider connected between a reference signal generator and a first controllable synchronous frequency divider. A second frequency divider is connected between a second controllable synchronous frequency divider and a voltage controlled oscillator. A phase-frequency comparator compares first and second low frequency signals from the first and second controllable synchronous frequency dividers and outputs an adjust signal according to a detected difference therebetween. A phase-locked detector outputs a phase-locked signal in response to the adjust signal. A switching control logic is operable so as to supply a frequency dividing control signal to the first and second controllable synchronous frequency dividers with reference to a divided reference signal from the first variable frequency divider upon receiving the phase-locked signal from the phase-locked detector.