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Phase synchronization method for extended partial response, and phase synchronization circuit and read channel circuit using this method
Phase synchronization method for extended partial response, and phase synchronization circuit and read channel circuit using this method
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机译:用于扩展部分响应的相位同步方法,以及使用该方法的相位同步电路和读取通道电路
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摘要
“100”, which is one of the (1, 7) RLL codes, is used as a clock acquisition pattern. After temporarily judging the sample output to be one of (1, −1), the phase error computing result for three samples (symbols) is added so as to cancel the errors of phase computing. Therefore the number of judgment states can be decreased, and phase can be acquired at high-speed even if the amplitude at acquisition has not been defined. At tracking, the sample output is judged to be one of three groups, [1+a, 1], 0, and [−1, −1−a]. Using the state transition of (1, 7) RLL codes, [1+a, 1] and [−1, −1−a] are distinguished. Since the number of judgment states decreases, judgment accuracy improves.
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