A “Wrapper” system and method are presented for integrating built-in self-test (BIST) and built-in self-repair (BISR) functions in a semiconductor memory device. The wrapper reduces the usual dependency of BISR circuitry on the BIST design, so that modifications and enhancements to the BIST may be made without requiring significant changes to the BISR. A generic BIST engine with an extended address range (spanning both the accessible and the redundant rows) is used to test the entirety of memory as a single array, preferably using a checkerboard bit pattern. The memory is tested in two stages, using the same BIST algorithm. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. At the end of the first stage a repair process allocates good redundant rows to replace faulty accessible rows. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored. Compared to existing methods, the new method is believed to greatly simplify the interface between the BIST and the BISR circuitry, reduce the overall size of test and repair circuitry, and provide improved test coverage.
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