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High IF frequencies with a lower frequency logic based FSK modulation selecting a harmonic alias and demodulation using sub-sampling techniques

机译:高IF频率和基于低频逻辑的FSK调制选择谐波别名并使用子采样技术进行解调

摘要

A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The 1-bit precision NCO includes an adder and a phase accumulator register which is clocked by a master clock signal. A two-input multiplexer has a single bit symbol value to generate BFSK, or larger input multiplexers can be implemented to provide M-ary FSK. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. Alternatively, the intermediate frequency may be arrived at without the need for upconversion by directly utilizing a harmonic alias at a desired IF frequency. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency. In the case where a sub-sampler in the 1-bit precision demodulator is not capable of operating at a required frequency (e.g., above 100 MHz or so), a harmonic sub-sampling mixer may be employed, with the resulting low IF signals being hard limited and lowpass filtered directly to the desired low IF. The received symbols are correlated with expected local frequencies representing a mark and a space. The correlation is integrated in an oversampled manner relative to the symbol interval. A decision is made as to which symbol was received using, e.g., a magnitude comparator.
机译:提供了具有成本效益的基于连续相位逻辑的调制器和解调器,以允许使用二进制频移键控(BFSK)和Mary FSK技术进行通信。 1位精度调制解调器体系结构的调制器基于1位精度数控振荡器(NCO),它相对于1位精度基于逻辑的调制器和/或解调器的频率提供了完整的可编程性。 1位精度NCO包括加法器和由主时钟信号提供时钟的相位累加器寄存器。两输入多路复用器具有单个位符号值以生成BFSK,或者可以实现更大的输入多路复用器以提供M进制FSK。使用简单的逻辑功能(即XNOR逻辑)将1位精度NCO的输出上变频至中频。可替代地,可以通过直接利用期望的IF频率处的谐波混叠来达到中频而无需上变频。可使用I / Q图像抑制来抑制上变频信号的不期望部分,和/或可以使用适当的带通滤波器。高IF的带限,硬限制信号作为接收IF信号提供给1位精度解调器,该信号被视为信号的1位量化。接收的IF信号被数字下变频为低IF信号,以产生低IF频率的混叠信号。如果1位精度解调器中的子采样器不能以所需的频率(例如,高于100 MHz左右)工作,则可以使用谐波子采样混频器,得到的低IF信号受到硬限制,并直接将低通滤波为所需的低IF。所接收的符号与表示标记和空格的预期局部频率相关。相对于符号间隔以过采样的方式对相关进行积分。使用例如幅度比较器来决定接收到哪个符号。

著录项

  • 公开/公告号US6674812B1

    专利类型

  • 公开/公告日2004-01-06

    原文格式PDF

  • 申请/专利权人 AGERE SYSTEMS INC.;

    申请/专利号US19990466837

  • 发明设计人 CARL R. STEVENSON;

    申请日1999-12-20

  • 分类号H04L271/20;

  • 国家 US

  • 入库时间 2022-08-21 23:12:34

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