A PARALLEL PROCESSING DECISION-FEEDBACK EQUALIZER (DFE) WITH LOOK-AHEAD PROCESSING

摘要

A method and apparatus are disclosed for increasing the effective processingspeed of a parallel decision-feedback equalizer by combining block processingand look-aheadtechniques in the selection (multiplexing) stage. The present inventionextends aparallel decision-feedback equalization by using look-ahead techniques in theselection stageto precompute the effect of previous blocks on each subsequent block, and tothereby removethe serial output dependency. The parallel decision-feedback equalizationincludes amultiplexor tree structure that selects an appropriate output value for eachblock andprecomputes the effect of previous blocks on each subsequent block. Amultiplexing delayalgorithm on the order of logN is employed to resolve the output dependencyand thus speedsup parallel block processing decision-feedback equalizations. The discloseddecision-feedbackequalization architecture can be combined with pipelining to completelyeliminatethe critical path problem. Pipelining reduces the required critical pathtiming to onemultiplexing time. The disclosed multiplexor tree circuitry for the paralleldecision-feedbackequalizer groups multiplexor blocks into groups of two, referred to as blockpairs, andprovides at least one multiplexor for each block, i, to select an outputvalue, y i, from amongthe possible precomputed values. The output of each parallel block depends onthe possibleprecomputed values generated by the look-ahead processors for the block, aswell as theactual values that are ultimately selected far each previous block. In orderto reduce the delayin obtaining each actual output value, the present invention assumes that eachblock containseach possible value, and carries the assumption through to all subsequentblocks. Thus, thenumber of multiplexors required to select from among the possible values growsaccording toN-logN, where N is the block number.