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TEST STRUCTURES FOR ELECTRICAL LINEWIDTH MEASUREMENT AND PROCESSES FOR THEIR FORMATION
TEST STRUCTURES FOR ELECTRICAL LINEWIDTH MEASUREMENT AND PROCESSES FOR THEIR FORMATION
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机译:电线宽度测量的测试结构及其形成过程
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摘要
In a method of determining a linewidth of a polysilicon line (16) formed by a lithographic process, a polysilicon layer is formed on a substrate. A line (16) is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure (14) is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line (16) and the polysilicion Van der Pauw structure (14) to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line (16) and the polysilicon Van der Pauw structure (14) and the dopant is activated. A sheet resistivity of the Van der Pauw structure (14) is determined, and the linewidth of the polysilicon line (16) is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure (14) as the sheet resistivity of the polysilicon line (16). A related test structure is also disclosed.
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机译:在确定通过光刻工艺形成的多晶硅线(16)的线宽的方法中,在基板上形成多晶硅层。使用所述光刻工艺从所述多晶硅层图案化线(16),并且从所述多晶硅层图案化范德堡结构(14)。然后将N> 2 <注入到多晶硅线(16)和多晶硅范德堡结构(14)中,以形成耗尽势垒。将P型掺杂剂注入到多晶硅线(16)和多晶硅范德堡结构(14)中,并激活掺杂剂。确定Van der Pauw结构(14)的薄层电阻率,然后使用Van der Pauw结构(14)的薄层电阻率作为电气电阻,通过电气线宽测量来确定多晶硅线(16)的线宽。多晶硅线(16)。还公开了相关的测试结构。
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