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Circuit and method for determing the phase difference between a sample clock and a sampled signal by linear approximation

机译:通过线性逼近确定采样时钟和采样信号之间的相位差的电路和方法

摘要

A phase-calculation circuit (46) includes a buffer (42), an approximation circuit (70), and an interpolator (56). The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit (70) linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator (56) calculates the absolute phase of that sample with respect to a predetermined point of the signal using the relative phase and the values of the first and second samples. The circuit is used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery circuit uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock and reduces the overall alignment-acquisition time.
机译:相位计算电路(46)包括缓冲器(42),近似电路(70)和内插器(56)。缓冲器接收并存储具有峰值幅度的周期性信号的第一和第二样本。逼近电路(70)线性地逼近周期信号的一部分,并计算信号部分内的采样之一的相对相位。内插器(56)使用相对相位以及第一和第二采样的值来计算该采样相对于信号的预定点的绝对相位。该电路用于减少数字定时恢复环路的对准获取时间,并允许缩短前同步码并相应增加磁盘的数据存储密度。该电路可以确定磁盘驱动器读取信号和读取信号采样时钟之间的初始相位差。数字定时恢复电路利用该相位差在读取信号和采样时钟之间提供初始的粗对准,并减少了总体的对准获取时间。

著录项

  • 公开/公告号EP1126617A3

    专利类型

  • 公开/公告日2003-11-12

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS INC.;

    申请/专利号EP20010300806

  • 发明设计人 OZDEMIR HAKAN;

    申请日2001-01-30

  • 分类号H03L7/091;G11B20/14;G11B20/10;

  • 国家 EP

  • 入库时间 2022-08-21 22:59:36

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