High-speed signal multiplexing circuit for multiplexing high-speed signals

摘要

In a high-speed signal multiplexing circuit, when data supplied to an input terminal (D₀-D₃) of a flip-flop circuit (13₀-13₃) differs from the data which has been latched in the flip-flop circuit (13₀-13₃), an exclusive OR circuit (14₀-14₃) supplies a control signal to a clock signal input terminal (CK₀-CK₃) of the flip-flop circuit (13₀-13₃). The flip-flop circuit (13₀-13₃) latches the data supplies to the input terminal (D₀-D₃) in response to the control signal. A data reading section (12) generates a read signal in synchronism with a clock signal. The data latched in the flip-flop circuit (13₀-13₃) is successively read out in response to the read signal.