High speed binary comparator circuit and High speed binary data comparison method

摘要

PURPOSE: A high speed binary comparator and a method for comparing high speed binary data are provided to reduce a layout area and a power consumption. CONSTITUTION: In the case that a clock signal(CLK) is the first status(for example, logical low), a PMOS(P-channel Metal-Oxide Semiconductor) transistor(10) executes a pull up of a node(NOD1) to a power voltage(VDD) level, and thus an output signal(F) of a binary comparator(100) becomes logical low. In the case that a clock signal(CLK) is the second status(for example, logical high), the binary comparator(100) receives inputted two 4-bit binary data(A,B), compares sizes of the binary data(A,B) therewith, and outputs the comparison result. An output signal(F) of the binary comparator(100) is '1'(the second status or logical high) or '0'(the first status or logical low). If the size of the binary data(A) is not more than that of the binary data(B), the output signal(F) of the binary comparator(100) is '1'. Otherwise, if the size of the binary data(A) is more than that of the binary data(B), the output signal(F) of the binary comparator(100) is '0'.