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Frequency multiplier and method of multiplying frequency of external clock output buffer of data and semiconductor device comprising the frequency multiplier and the output buffer
Frequency multiplier and method of multiplying frequency of external clock output buffer of data and semiconductor device comprising the frequency multiplier and the output buffer
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机译:倍频器和将数据的外部时钟输出缓冲器的倍频的方法以及包括倍频器和输出缓冲器的半导体装置
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摘要
PURPOSE: A clock frequency multiplier of an external clock and its method, and an output buffer of data and a semiconductor device comprising the multiplier and the output buffer are provided to multiply the external clock having a low clock frequency to a high clock frequency. CONSTITUTION: According to the frequency multiplier(810) outputting an internal clock by multiplying an external clock having a fixed frequency, the first pulse signal generator circuit receives the first clock signal and the second clock signal having an equal frequency and generates the first pulse signal having the first pulse width when a level of the first clock signal becomes higher than a level of the second clock signal. The second pulse signal generator circuit is enabled in response to the first control signal, and receives a reference voltage and the first clock signal, and outputs the second pulse signal having the second pulse width when a level of the reference voltage becomes higher than the level of the first clock signal. And a logic OR circuit receives the first pulse signal and the second pulse signal, and outputs the internal clock by performing a logic OR operation as to the first and the second pulse signal.
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