首页> 外国专利> Frequency multiplier and method of multiplying frequency of external clock output buffer of data and semiconductor device comprising the frequency multiplier and the output buffer

Frequency multiplier and method of multiplying frequency of external clock output buffer of data and semiconductor device comprising the frequency multiplier and the output buffer

机译:倍频器和将数据的外部时钟输出缓冲器的倍频的方法以及包括倍频器和输出缓冲器的半导体装置

摘要

PURPOSE: A clock frequency multiplier of an external clock and its method, and an output buffer of data and a semiconductor device comprising the multiplier and the output buffer are provided to multiply the external clock having a low clock frequency to a high clock frequency. CONSTITUTION: According to the frequency multiplier(810) outputting an internal clock by multiplying an external clock having a fixed frequency, the first pulse signal generator circuit receives the first clock signal and the second clock signal having an equal frequency and generates the first pulse signal having the first pulse width when a level of the first clock signal becomes higher than a level of the second clock signal. The second pulse signal generator circuit is enabled in response to the first control signal, and receives a reference voltage and the first clock signal, and outputs the second pulse signal having the second pulse width when a level of the reference voltage becomes higher than the level of the first clock signal. And a logic OR circuit receives the first pulse signal and the second pulse signal, and outputs the internal clock by performing a logic OR operation as to the first and the second pulse signal.
机译:目的:提供外部时钟的时钟频率倍增器及其方法,以及数据的输出缓冲器和包括该乘法器和输出缓冲器的半导体器件,以将具有低时钟频率的外部时钟乘以高时钟频率。组成:根据倍频器(810)通过将具有固定频率的外部时钟乘以输出内部时钟,第一脉冲信号发生器电路接收具有相同频率的第一时钟信号和第二时钟信号并产生第一脉冲信号当第一时钟信号的电平变得高于第二时钟信号的电平时,具有第一脉冲宽度。第二脉冲信号发生器电路响应于第一控制信号而被使能,并且接收参考电压和第一时钟信号,并且当参考电压的电平变得高于该电平时,输出具有第二脉冲宽度的第二脉冲信号。第一个时钟信号的逻辑或电路接收第一脉冲信号和第二脉冲信号,并通过对第一和第二脉冲信号执行逻辑或运算来输出内部时钟。

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