Low capacitance, low kickback noise input stage of a multi-level quantizer with dithering and multi-threshold generation for a multi-bit sigma-delta modulator

摘要

An N-level quantizer circuit has an analog input terminal and N-1 digital output terminals, and includes a sampling circuit coupled to the input terminal for providing a sampled input voltage signal; at least one preamplifier stage for converting the sampled input voltage signal to a current signal and providing an amplified sampled input signal; and N-1 comparator stages each having an input coupled to an output of the at least one preamplifier stage and sharing the input current equally. Individual ones of the N-1 comparator stages operate to compare the amplified sampled signal to an associated one of N-1 reference signals. The quantizer further includes N-1 latches, individual ones of which latch an output state of one of the N-1 comparators and have an output coupled to one of the N-1 digital output terminals of the quantizer circuit. Individual ones of the N-1 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise from the N-1 latches to others of the comparators and to the input terminal of the quantizer circuit. In one embodiment the use of a common preamplifier stage also serves to reduce the input capacitance of the quantizer, thereby reducing the capacitive load seen by the output amplifier, which may be an integrator, of the loop filter. The quantizer further includes a dither signal generator having an output coupled to the output of the at least one preamplifier stage, and a threshold signal generator outputting the N-1 reference signals. The threshold signal generator may be simply constituted using a string of series coupled resistances connected between positive and negative reference voltages, or a transconductor feeding scaled current mirrors can be employed.