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Delay locked loop of a semiconductor memory device having the improved compensation delay circuit and the delay time compensation method

机译:具有改进的补偿延迟电路和延迟时间补偿方法的半导体存储装置的延迟锁定环

摘要

PURPOSE: A DLL of a semiconductor memory device having an improved compensation delay circuit and a method for compensating delay time about the same are provided to compensate a data output delay time accurately by a data output driver. CONSTITUTION: According to a DLL(Delay Locked Loop)(70) generating an internal clock by being synchronized to an external clock, a phase detector(72) detects a phase error between the external clock and the internal clock, and outputs a phase error signal thereof. A low pass filter(73) outputs a control signal in response to the phase error signal. A variable delay circuit(74) varies its delay time in response to the control signal, and generates the internal clock by performing locking by delaying a phase of the external clock according to the varied delay time. A compensation delay circuit(75) delays a phase of the internal clock for the first delay time and then outputs it to the phase detector, in order to compensate the delay time until data is output to the external of the semiconductor memory device in a memory cell array.
机译:目的:提供一种具有改进的补偿延迟电路的半导体存储器件的DLL和一种用于补偿该DLL的延迟时间的方法,以通过数据输出驱动器精确地补偿数据输出延迟时间。构成:根据DLL(延迟锁定环)(70),该DLL通过与外部时钟同步来产生内部时钟,相位检测器(72)检测外部时钟和内部时钟之间的相位误差,并输出相位误差其信号。低通滤波器(73)响应于相位误差信号而输出控制信号。可变延迟电路(74)响应于控制信号而改变其延迟时间,并且通过根据改变后的延迟时间延迟外部时钟的相位来执行锁定,从而生成内部时钟。补偿延迟电路(75)将内部时钟的相位延迟第一延迟时间,然后将其输出到相位检测器,以便补偿延迟时间,直到数据输出到存储器中的半导体存储器件的外部为止单元阵列。

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