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Delay locked loop of a semiconductor memory device having the improved compensation delay circuit and the delay time compensation method
Delay locked loop of a semiconductor memory device having the improved compensation delay circuit and the delay time compensation method
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机译:具有改进的补偿延迟电路和延迟时间补偿方法的半导体存储装置的延迟锁定环
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摘要
PURPOSE: A DLL of a semiconductor memory device having an improved compensation delay circuit and a method for compensating delay time about the same are provided to compensate a data output delay time accurately by a data output driver. CONSTITUTION: According to a DLL(Delay Locked Loop)(70) generating an internal clock by being synchronized to an external clock, a phase detector(72) detects a phase error between the external clock and the internal clock, and outputs a phase error signal thereof. A low pass filter(73) outputs a control signal in response to the phase error signal. A variable delay circuit(74) varies its delay time in response to the control signal, and generates the internal clock by performing locking by delaying a phase of the external clock according to the varied delay time. A compensation delay circuit(75) delays a phase of the internal clock for the first delay time and then outputs it to the phase detector, in order to compensate the delay time until data is output to the external of the semiconductor memory device in a memory cell array.
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