DIGITAL LOCK DETECTING CIRCUIT, ESPECIALLY FOR DETECTING WHETHER A CARRIER FREQUENCY IS SYNCHRONIZED DURING A QUADRATURE PHASE SHIFT KEYING(QPSK) DEMODULATION

摘要

PURPOSE: A digital lock detecting circuit is provided to use an absolute value and a gain change while employing adding, subtracting, and comparing apparatuses only, and to equivalently realize the gain change by using a shifter and an adder, thereby reducing an amount of calculation. CONSTITUTION: A lock detector(200) comprises as follows. The first operator(210) receives two different channel signals from a QPSK demodulator(100), subtracts absolute values produced by subtracting the two signals from absolute values produced by adding the two signals, and obtains absolute values again. The second operator(220) receives the two different channel signals to obtain absolute values, respectively, and obtains absolute values again for a difference signal of the obtained absolute values. A divider(230) divides outputs of the first operator(210) into preset values. A detector(240) obtains difference values between output values of the divider(230) and output values of the second operator(220), and detects whether receiving signals are synchronized from the accumulated difference values.