Digit-serial systolic multiplier for finite fields

摘要

PURPOSE: A digit serial systolic multiply on a finite field is provided to execute an index conversion of a data dependence graph with respect to an LSB(Least Significant Bit)-first multiplication algorithm, divide the graph into a digit size, project the graph, and obtain an SFG(Signal Flow Graph) array by constituting a systolic multiply of a digital serial structure using an LSB(Least Significant Bit)-first algorithm on a finite field. CONSTITUTION: A 'P'(1=P=N) processor responds to a control signal inputted from the "P-1" processor. A calculation unit of the processor calculates Ai, Bi, Gi, and Pi values of 'L' bit inputted from the "P-1" processor. The data are calculated continuously through the same formula in the "P-1" processor. Processors(10,20,30,40) include a processing circuit of an identical calculation method. In the case that data are divided and processed as a digit unit, the number of processor is a value obtained by dividing the data by a digit size. Each processor(10,20,30,40) comprises a calculation unit, a storing unit, and an input gate. The calculation unit includes the "LxL" number of cells and latches and executes an actual multiplication with respect to data of 'L' bit. The cell is a module for processing a bit. The storing unit includes a control signal latch for storing a control signal. The input gate processes an input value.