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Data processing device has memory registers configured in a shift register chain with access to the registers configured so that data processing units can access only the first and last registers in the chain
Data processing device has memory registers configured in a shift register chain with access to the registers configured so that data processing units can access only the first and last registers in the chain
Data processing device with memory registers (3), at least a processing unit (1) and at least a switching unit (2) that is connected to a processor unit and the memory register. At least one processing unit has read-write access to a memory register, with at least two memory registers connected to at least one shift register chain (4-6). The data processing device is configured so that the at least one processing unit that has access to a memory register forming part of a shift register chain can only access the first and last shift registers within the chain. An Independent claim is made for a method for controlling access to a shift register chain by at least a data processing unit of a data processing device.
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