Burst access to coprocessors for data transfer between CPU, cache, peripheral units involves program-initiated mirroring between cache memory, coprocessor using coprocessor selection controller

摘要

The method involves a cache controller controlling the temporary storage of processor data, providing a Ping-Pong buffer at least in a first or second coprocessor, providing first and second D-cache sets in the data cache associated with the cache memory, in which data accesses are carried out by the cache controler as burst accesses, program-initiated mirroring between the cache memory and a coprocessor using a coprocessor selection controller. The method involves a cache controller (3) controlling the temporary storage of processor data, providing a Ping-Pong buffer (4) at least in a first or second coprocessor (10,11), providing first and second D-cache sets (6,16) in the data cache associated with the cache memory (21), in which data accesses are carried out by the cache controler as burst accesses, program-initiated mirroring between the cache memory and the first or second coprocessor using a coprocessor selection controller (14).