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SMBus message handler, has finite state machine which receives and interprets instruction and handles data transfer between SMBus interface and register set
SMBus message handler, has finite state machine which receives and interprets instruction and handles data transfer between SMBus interface and register set
The message handler has a memory for storing a micro-code with at least two programs for handing respective bus command protocol and include at least one instruction respectively. A register interface identifies a START address of the program in the memory. An instruction calling unit reads an instruction at an address specified by a program counter. A finite state machine receives the instruction and interprets it to handle the data transfer between an SMBus interface and a register set, in accordance with the instructions read from the memory. Independent claims are included for an integrated circuit chip for transmitting and receiving data via an SMBus; and for a method of controlling an SMBus.
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