首页> 外国专利> Test circuit for large scale integration, has block determination unit that outputs determination result signal to be input to selection unit along with reference and control signals, when signals with equal bits are input

Test circuit for large scale integration, has block determination unit that outputs determination result signal to be input to selection unit along with reference and control signals, when signals with equal bits are input

机译:用于大规模集成的测试电路,具有块确定单元,当输入相等比特的信号时,该块确定单元将确定结果信号与参考信号和控制信号一起输出到选择单元

摘要

A block determination unit (310) in block testing unit (301) outputs a determination result signal (335) to be input to selection unit (315) along with reference and control signals (RS,334), when signals (331,333) with equal bits are input. The signals (337) from the block testing units are input to a logic processing unit (303) that outputs a comprehensive determination result signal (338). An independent claim is also included for semiconductor device.
机译:当信号(331,333)相等时,块测试单元(301)中的块确定单元(310)输出要与参考信号和控制信号(RS,334)一起输入到选择单元(315)的确定结果信号(335)。位被输入。来自块测试单元的信号(337)被输入到逻辑处理单元(303),该逻辑处理单元输出综合确定结果信号(338)。对于半导体器件也包括独立权利要求。

著录项

  • 公开/公告号DE102004004308A1

    专利类型

  • 公开/公告日2004-09-02

    原文格式PDF

  • 申请/专利权人 NEC ELECTRONICS CORP. KAWASAKI;

    申请/专利号DE20041004308

  • 发明设计人 TERAUCHI YOUJI;

    申请日2004-01-28

  • 分类号G11C29/00;G11C16/00;

  • 国家 DE

  • 入库时间 2022-08-21 22:43:07

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