single chip - microcomputer with a memory controller

摘要

PROBLEM TO BE SOLVED: To provide a microcomputer with which the access conditions of a built-in memory can be flexibly changed. ;SOLUTION: A read only memory (ROM) bus 22, random access memory (RAM) bus 26 and IO bus 30 for inputting/outputting independent data from these buses 22 and 26 are connected to a central processing unit (CPU) 12 having an instruction processing part 50 and a data processing part 60. A reloadable register 72 installed inside a memory access control circuit 70 is stored with the set value of wait cycle number related to ROM access, the set value of wait cycle number related to RAM access, and set value for switching the input path of the data processing part 60. These set values are changed corresponding to the cycle time of an internal clock signal (CPU lock signal) ICLK. Corresponding to these set values, the insertion of wait cycles at the respective instruction processing part 50 and data processing part 60 is controlled and it is selected whether or not the input of the data processing part 60 is to be latched.;COPYRIGHT: (C)1997,JPO