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integrated halbleiterschaltung measuring and digital tensioning of the schwellenspannung of transistors and related methods

机译:集成的halbleiterschaltung测量和数字拉伸的晶体管schwellenspannung及其相关方法

摘要

An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of high to low reference voltage values. The MOSFETs are biased to have a desired effective threshold voltage based upon the plurality of comparison signals. Logic decoding circuits accept the plurality of comparison signals and generate at least one bias control signal. Bias circuits are responsive to the at least one bias control signal for generating a desired bias voltage from among a plurality of bias voltages having a spread of high to low bias voltage values to thereby bias the plurality of MOSFETs to the desired effective threshold voltage. Method aspects of the invention are also disclosed. IMAGE
机译:集成电路在衬底上包括多个MOSFET。多个感测MOSFET用于基于将与感测到的初始阈值电压有关的信号与从高参考电压值到低参考电压值的范围的相应参考电压进行比较来生成多个比较信号。基于多个比较信号,将MOSFET偏置为具有期望的有效阈值电压。逻辑解码电路接收多个比较信号并产生至少一个偏置控制信号。偏置电路响应于至少一个偏置控制信号,以从具有高到低偏置电压值的扩展的多个偏置电压中生成期望的偏置电压,从而将多个MOSFET偏置到期望的有效阈值电压。还公开了本发明的方法方面。 <图像>

著录项

  • 公开/公告号DE69728117D1

    专利类型

  • 公开/公告日2004-04-22

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS INC.;

    申请/专利号DE19976028117T

  • 发明设计人 SUICHEONG SO JASON;CHAN TSIU CHIU;

    申请日1997-11-27

  • 分类号G05F3/24;G05F3/20;

  • 国家 DE

  • 入库时间 2022-08-21 22:40:38

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