首页> 外国专利> Methods and apparatus for detecting data collision of data on a data bus in case of out-of-order memory accesses or different times of memory access execution

Methods and apparatus for detecting data collision of data on a data bus in case of out-of-order memory accesses or different times of memory access execution

机译:用于在无序存储器访问或存储器访问执行时间不同的情况下检测数据在总线上的数据冲突的方法和装置

摘要

A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.
机译:描述了一种在多存储体存储设备中使用存储体标签寄存器来避免后台操作冲突的方法。存储控制器包括多个存储体寄存器,每个存储体都与多个存储体之一相关联,其中存储体寄存器被布置为存储信息,存储体编号,存储体状态和特定存储体的存储体计数器。 。存储器控制器还包括耦合到每个存储体寄存器的可调存储体比较器。存储器控制器接收输入的系统地址请求,该请求包括请求的存储号。所请求的存储体编号用于将可调存储体比较器配置为具有特定的存储体工作特性,以定位存储体寄存器,并确定所请求的存储体的存储体状态和存储体进入状态。当存储库条目状态将请求的存储库标识为打开时,将访问请求的存储库。

著录项

  • 公开/公告号GB2359164B

    专利类型

  • 公开/公告日2003-12-03

    原文格式PDF

  • 申请/专利权人 * INFINEON TECHNOLOGIES AG;

    申请/专利号GB20010011923

  • 发明设计人 HENRY * STRACOVSKY;PIOTR * SZABELSKI;

    申请日1999-11-15

  • 分类号G06F12/00;G06F9/30;G06F9/38;G06F13/28;G06F13/36;

  • 国家 GB

  • 入库时间 2022-08-21 22:38:24

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