Vector permutation in single-instruction multiple-data processor which is controlled by parameters stored in control registers accessed via a control block

摘要

Disclosed is an arrangement and system for vector permutation in single-instruction multiple-data (SIMD) processors 100 which is controlled by control parameters 140 stored in control registers 141, 142, 143 accessed via a control block 145. A permutation logic block 120 receives vectors from vector registers 110 and permutates them according to control parameters supplied by control registers. The plurality of control registers are coupled to the logic block via a control means which selects and provides the control register to be used by the logic block. The arrangement could include a negate block 130 coupled to the control block and the logic block to receive the vectors from the logic block. The control means could include a counter 150 arranged to provide a sequential order for selecting the control registers. The sequential order could include automatic sequencing though a set of fixed control parameters and could be cyclical.