METHOD OF GENERATING DELAY TROUBLE TEST PATTERN FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD OF INSPECTING DELAY TROUBLE THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a method of generating a test pattern capable of conducting a dynamic test for each path in a semiconductor integrated circuit including a memory circuit.;SOLUTION: An objective trouble is selected from a data line of the memory circuit (step 101), the longest test-allowable path corresponding to the selected objective trouble is selected (step 102), an initialization pattern (step 103) and a transition pattern (step 104) of the longest test-allowable path are found, an initialization pattern (step 105) and a transition pattern (step 106) of an address line are found, an initialization pattern (step 107) and a transition pattern (step 108) of a control signal group are found, a value provided by reading out a value written in the memory circuit into an output set value scanning FF group is found as an expected value (step 109), and the patterns found in the steps 103-109 are generated as a serial pattern (step 110).;COPYRIGHT: (C)2005,JPO&NCIPI