SINGLE CHIP VLSI IMPLEMENTATION OF DIGITAL RECEIVER EMPLOYING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING

摘要

PPROBLEM TO BE SOLVED: To provide a device which is highly integrated and realized on a single VLSI chip at a low cost for receiving a digital broadcast such as a terrestrial digital video broadcast. PSOLUTION: Improved channel estimation and correction circuits are provided. The receiver has highly accurate sampling rate control and frequency control circuits. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to a resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements. PCOPYRIGHT: (C)2005,JPO&NCIPI