METHOD OF HDL SIMULATION CONSIDERING HARD MACRO CORE LIBRARY WITH NEGATIVE SETUP/HOLD TIME

摘要

PPROBLEM TO BE SOLVED: To provide a method of HDL simulation for a hard macro core library with a negative setup time or negative hold time. PSOLUTION: When the negative setup time is present in a timing model, it is decided whether or not there is an electronic circuit element for receiving a signal to be input through an input terminal having the negative setup time. When there is the electronic circuit element, a first electronic circuit element having the same setup time as the electronic circuit element and operating in response to a signal which the identical phase with a clock signal to be input to the electronic circuit element is generated, and a new library including the hard macro core library and the first electronic circuit element is generated. By the new library thus generated, it is possible to check the timing of the hard macro core library having the negative setup/hold time while HDL simulation is being executed. PCOPYRIGHT: (C)2005,JPO&NCIPI