Memory cells not affected by the heavy ion collisions

摘要

(57) Abstract The differential memory electrolysis cell, respectively, includes with high supply voltage and low the 1st P channel transistor and the 2nd N channel transistor and the 3rd N channel transistor which is in series jointed between supply voltage, two sets are had. The gate of one N channel transistor of each set is jointed to the output node of set of another side. The gate of the other N channel transistor of each set is jointed to the gate of the 1st transistor of the same set. The 4th P channel transistor is joined by each set, is jointed between the gates of the 1st transistor of high tension and aforementioned set. The 5th P channel transistor is joined by each set, the gate of the 1st transistor of aforementioned set reads and/the writing belt or is jointed between voltage low.