Integrated type test of the Syrian riser/deci- rear riser inside FPGA

摘要

The field programmable gate array (FPGA) device includes the high-speed Syrian riser/the deci- rear riser (SERDES). Depending upon this field programmable gate array, at operating speed, the program possible built-in test of SERDES becomes possible. By the digital clock manager circuit, the clock pulse is connected, in order to apply load on the SERDES circuit. Forming test pattern, in order to analyze the data which is received by the SERDES circuit, to program it is possible the logic array of FPGA. It is possible also to form the cyclic redundancy check (CRC) character or the other error detection character, making use of logic array. FPGA while the test does the large-scale test in the telecommunication line, can remember the result of that test. Without spending test time substantially, or the complicated test device the tester of the dying and outside can read out the result of the test. After the test completes, again this device can be programmed in order to execute end user function without focusing what cost on the device in order to do the test.