Design manner of the dummy pattern which accompanies grinding process, it is formed to the wiring layer of the record media null semiconductor equipment which records

摘要

PROBLEM TO BE SOLVED: To efficiently design a dummy pattern to be formed on a wiring layer for eliminating the surface step of polished surfaces after a chemical mechanical polishing(CMP) process in a production process of semiconductor device.;SOLUTION: The correction value of pattern density is determined on the basis of allowable pattern density derived from the request of inter-wiring capacity reduction and proper pattern density derived from the request of surface step reduction on the polished surfaces. Further, it is verified by simulation whether the surface step of the polished surfaces is settled within an allowable range or not when the dummy pattern is formed so that the corrected pattern density can be provided and when the step is out of the allowable range, by repeating similar processing, the pattern density satisfying two requests in good balance is determined.;COPYRIGHT: (C)2003,JPO