Data transfer manner, data reception manner and parallel computer system null multiple treatment

摘要

PROBLEM TO BE SOLVED: To provide an inter-processor data transfer system which can designate a body storage area via a receiving processor in a parallel computer system where plural processors are connected to a switch circuit and a transmitting processor transmits a packet header to the switch circuit to send the header and the body data to the receiving processor via the switch circuit. SOLUTION: The selection information is added into a packet header 2 to decide an address designated in the header 2 or a message area 3a designated by a receiving processor PE as an area where the body data 3 corresponding to the header 2 are stored. The processor PE contains a selection means to select the storage position of the data 3 and switches this selection means based on the selection information on the header 2 to store the data 3 in the address designated by a transmitting processor or the area 3a designated by the processor PE.