首页> 外国专利> Unified serial/parallel concatenated convolutional code decoder architecture and method

Unified serial/parallel concatenated convolutional code decoder architecture and method

机译:统一的串行/并行级联卷积码解码器体系结构和方法

摘要

A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.
机译:具有两种操作模式的turbo解码器根据N状态Radix-K网格来解码接收到的信息,其中N和K是等于或大于1的整数。 Turbo解码器使用串联寻址技术,该技术可使其在第一工作模式下充当串行卷积码解码器,在第二工作模式下充当并行卷积码解码器。解码器使用行内寻址技术,允许它在处理接收到的信息时使用同一内存块来存储和检索网格状态。 Turbo解码器还可以按照N状态Radix-K网格进行操作,其中N是等于2或更大的整数,K是等于4或更大的整数。

著录项

  • 公开/公告号US2005010854A1

    专利类型

  • 公开/公告日2005-01-13

    原文格式PDF

  • 申请/专利权人 MARK ANDREW BICKERSTAFF;

    申请/专利号US20030608831

  • 发明设计人 MARK ANDREW BICKERSTAFF;

    申请日2003-06-26

  • 分类号H03M13/00;

  • 国家 US

  • 入库时间 2022-08-21 22:25:33

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