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Processor with scheduler architecture supporting multiple distinct scheduling algorithms

机译:具有调度程序架构的处理器,支持多种不同的调度算法

摘要

A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm. Association of a given one of the transmission elements with a particular one of the second table entries establishes a scheduling rate for that transmission element. The scheduler maintains a second table pointer identifying a current one of the second table entries that is eligible for transmission.
机译:处理器包括调度器,该调度器用于利用至少第一表和第二表来调度数据块以从多个队列或其他传输元件进行传输。所述第一表可以包括与第一和第二先进先出(FIFO)列表相对应的条目的列表,所述条目对应于要根据第一调度算法(例如加权公平排队调度算法)为其调度数据块的传输元素。 。调度器维护第一表指针,该第一表指针将第一表的第一列表和第二列表中的至少一个识别为优先于第一表的第一列表和第二列表中的另一个。第二表包括对应于要根据第二调度算法(例如恒定比特率或可变比特率调度算法)为其调度数据块的传输元件的多个条目。给定的一个传输元件与第二个表项中的特定一个的关联建立了该传输元件的调度速率。调度器维护第二表指针,该第二表指针标识第二表项中的当前一个适于传输的表项。

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