Data-enabled static flip-flop circuit with no extra forward-path delay penalty

摘要

A logic circuit includes a data-enable controller for outputting a data value. When implemented as a master-slave flip-flop, a data enable signal controls the activation of a master stage of the flip-flop in conjunction with the transitioning edge of an input clock signal. The data enable signal also controls the feedback of a logical value stored in the slave stage to a storage node of the master stage. Operation of the slave stage may be controlled by the input clock signal only. Through this structural configuration, the flip-flop or latch outputs logical values without requiring any additional forward-path delay elements. As a result, these devices are faster and more efficient than conventional circuits.