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Method and system for terminating unnecessary processing of a conditional instruction in a processor

机译:在处理器中终止对条件指令的不必要处理的方法和系统

摘要

A method and system for terminating unnecessary processing of at least one multi-clock conditional instruction in a processor. The conditional instruction is processed through a processing pipeline including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. It is determined whether the conditional instruction is executable in the execute stage based on whether one or more conditions are fulfilled. If the conditional instruction is being processed in both the decode and execute stages, the conditional instruction is terminated in the decode stage if the conditional instruction is not to be executed in the execute stage. The conditional instruction may also be terminated in the intermediate processing stages. Early termination of such a conditional instruction saves processing resources and reduces power consumption of the processor.
机译:一种用于终止处理器中至少一个多时钟条件指令的不必要处理的方法和系统。通过处理管线来处理条件指令,该处理管线至少包括解码级,执行级以及在它们之间的一个或多个中间处理级。基于是否满足一个或多个条件,确定条件指令在执行阶段是否可执行。如果在解码和执行阶段都在处理条件指令,则如果在执行阶段不执行条件指令,则在解码阶段终止条件指令。条件指令也可以在中间处理阶段终止。这种条件指令的提早终止节省了处理资源并减少了处理器的功耗。

著录项

  • 公开/公告号US2004255103A1

    专利类型

  • 公开/公告日2004-12-16

    原文格式PDF

  • 申请/专利权人 VIA-CYRIX INC.;

    申请/专利号US20030459283

  • 发明设计人 RICHARD L. DUNCAN;CHARLES F. SHELOR;

    申请日2003-06-11

  • 分类号G06F9/44;

  • 国家 US

  • 入库时间 2022-08-21 22:23:15

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