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CLASS AB OPERATIONAL AMPLIFIER WITH SPLIT FOLDED-CASCODE STRUCTURE AND METHOD

机译:折叠式层叠码结构的AB类运算放大器和方法

摘要

Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor. The bias current is sensed and compared with a reference current to produce an error signal that is amplified to produce a differential error current a signal which is introduced applied to sources of the first and second cascode transistors.
机译:通过为放大器的输入级( 2 )的输出和输出( 17,18 )提供相等的放大,可以控制AB类输出级的输出晶体管中的偏置电流。 AB类控制电路( 46 )的B>)。用于差分输入级( 2 )的第一侧的分离输入晶体管电路结构包括第一( 15 )和第二( 16 )输入晶体管的栅极耦合到第一输入(Vin +)。输入级的第三输入晶体管( 10 )的栅极耦合至第二输入(Vin&min;)。分体折叠式共栅共源共栅电路包括第一( 25 )和第二( 30 )共源共栅晶体管,其漏极分别耦合到输出晶体管的栅极,第三共源共栅晶体管的源极耦合到第三输入晶体管的漏极。偏置电流被感测并且与参考电流比较以产生误差信号,该误差信号被放大以产生差分误差电流,该信号被引入施加到第一和第二共源共栅晶体管的源极。

著录项

  • 公开/公告号US2004257160A1

    专利类型

  • 公开/公告日2004-12-23

    原文格式PDF

  • 申请/专利权人 WANG BINAN;

    申请/专利号US20030465184

  • 发明设计人 BINAN WANG;

    申请日2003-06-19

  • 分类号H03F3/45;

  • 国家 US

  • 入库时间 2022-08-21 22:23:00

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