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Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit

机译:包括通过晶体管和CMOS电路的组合的逻辑电路以及该逻辑电路的合成方法

摘要

To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant 1 or 0 is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.
机译:为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来生产具有极佳特性(包括面积,延迟时间和功耗)的逻辑电路,可通过布尔函数创建二进制决策图。各个节点映射到2输入,1输出,1控制输入传输晶体管选择器,以合成传输晶体管逻辑电路。通过晶体管的两个输入(不包括控制输入)中的任何一个固定为逻辑常数1或0的NAND或NOR逻辑的传输晶体管选择器,被替换为逻辑上与NAND或NOR逻辑相同的CMOS门代替如果通过替换获得的预定电路特性的值接近最佳值,则通过晶体管选择器。

著录项

  • 公开/公告号US6820242B2

    专利类型

  • 公开/公告日2004-11-16

    原文格式PDF

  • 申请/专利权人 RENESAS TECHNOLOGY CORP.;

    申请/专利号US20020178216

  • 发明设计人 SHUNZO YAMASHITA;KAZUO YANO;

    申请日2002-06-25

  • 分类号G06F175/00;

  • 国家 US

  • 入库时间 2022-08-21 22:21:01

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