Visual program memory hierarchy optimization

摘要

In general, and in a form of the present invention, a method is provided for reducing execution time of a program executed on a digital system by improving hit rate in a cache of the digital system. This is done by determining cache performance during execution of the program over a period of time as a function of address locality, and then identifying occurrences of cache conflict between two program modules. One of the conflicting program modules is then relocated so that cache conflict is eliminated or at least reduced. In one embodiment of the invention, a 2D plot of cache operation is provided as a function of address versus time for the period of time. A set of cache misses having temporal locality and spatial locality is identified as a horizontally arranged grouping of pixels at a certain address locality having a selected color indicative of a cache miss. Cache conflict is determined by overlying an interference grid or a shadow grid on the plot responsive to the address locality such that a plurality of lines are displayed at other address localities that map to the same region in cache as the first address locality. In order to relocate a program module, a relocation parameter is provided to a linker to cause the program module to be linked at a different address.