Utilizing slow ASIC logic BIST to preserve timing integrity across timing domains

摘要

A logic built-in self-test controller is disclosed. The invention, in its various aspects and embodiments, is a built-in self-test controller capable of performing a logic built-in self-test at a test frequency at least as slow as a slowest frequency of a plurality of timing domains to undergo the logic built-in self-test. A method for performing a built-in self-test on an integrated circuit device.