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Method for increasing rate at which a comparator in a metastable condition transitions to a steady state

机译:在亚稳态条件下比较器转换到稳态的速率增加的方法

摘要

A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
机译:一种用于减少具有比较器阵列的模数转换器中的位错误的方法。第一和第二比较器的输出作为“异或”门的输入被接收。第一和第二比较器在阵列中被第三比较器分开。异或门的输出用于确定第三个比较器是否处于亚稳态。如果第三比较器处于亚稳态,则增加第三比较器的锁存电路的偏置电流,以增加第三比较器转变为稳态的速率。

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