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Automatic synthesis script generation for synopsys design compiler
Automatic synthesis script generation for synopsys design compiler
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机译:synopsys设计编译器的自动综合脚本生成
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摘要
A method of generating synthesis scripts to synthesize integrated circuit (IC) designs described in a generic netlist into a gate-level description includes the steps of identifying hardware elements in a generic netlist, determining key pins for each of the identified hardware elements, extracting design structure and hierarchy from the generic netlist, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design, and generating script to cause a logic synthesis tool to repeat these bottom-up and top-down applications until constraints are satisfied.
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