首页> 外国专利> DIGITAL-PHASE TO DIGITAL AMPLITUDE TRANSLATOR WITH FIRST BIT OFF PRIORITY CODED OUTPUT FOR INPUT TO UNIT WEIGHED DIGITAL TO ANALOG CONVERTER

DIGITAL-PHASE TO DIGITAL AMPLITUDE TRANSLATOR WITH FIRST BIT OFF PRIORITY CODED OUTPUT FOR INPUT TO UNIT WEIGHED DIGITAL TO ANALOG CONVERTER

机译:具有第一位优先级编码输出的数字相到数字放大器转换器,用于将加权的数字量输入到模拟转换器

摘要

Differential heating is avoided by a digital to analog converter for generating analog cyclical waveforms having a period. The cyclical waveforms are generated by conversion of a sequence of step wise linearly incrementing digital phase words presented during the period for conversion. The digital to analog converter has a clock 620 for operating conversion timing within the digital to analog converter. The clock 620 generates a clock pulse for conversion of each of the digital phase words by said digital to analog converter while generating the cyclical waveform. A lookup read only memory 606 for converting each of the incrementing digital phase words within the period into a plurality of ON commands to be used by a plurality of current sources 612. The plurality of ON commands are timed to gener­ate the cyclical waveforms and have nearly equal time duration approximating a 50 percent duty cycle. A first exclusive - OR 608 circuit has a first input, a second input and an output. The first input is connected to the sequence of ON commands generated from the lookup table. The sequence of ON commands is generated using a second exclusive OR circuit 618 and a unary decoder 610. A buffer 612 stores the output from the first exclusive - OR circuit for the duration of each clock cycle. The buffer drives the current sources thereby activating each of the current sources for nearly equal time intervals during the period. A summer 614 sums the current sources into a sum of currents. A current to voltage converter converts the sum of currents into an output voltage, the output voltage generating the cyclical waveform. The cyclical waveform has one or more non-linear portions reflected in the content of the read only memory 606.
机译:通过用于产生具有周期的模拟周期性波形的数模转换器避免了差动加热。通过转换在转换期间出现的一系列逐步线性递增的数字相位字来生成周期性波形。数模转换器具有时钟620,用于操作数模转换器内的转换定时。时钟620产生时钟脉冲,以通过所述数模转换器转换每个数字相位字,同时产生循环波形。查找只读存储器606,用于将周期内的每个递增数字相位字转换为多个ON命令,以供多个电流源612使用。对多个ON命令进行计时以生成周期性波形,并且具有几乎相等的持续时间,占空比约为50%。第一异或门608电路具有第一输入,第二输入和输出。第一个输入连接到从查找表生成的ON命令序列。使用第二异或电路618和一元解码器610生成ON命令的序列。缓冲器612在每个时钟周期的持续时间内存储来自第一异或电路的输出。缓冲器驱动电流源,从而在该时段内以几乎相等的时间间隔激活每个电流源。求和器614将电流源求和成电流总和。电流至电压转换器将电流之和转换为输出电压,该输出电压生成周期性波形。循环波形具有反映在只读存储器606的内容中的一个或多个非线性部分。

著录项

  • 公开/公告号WO2004082146A8

    专利类型

  • 公开/公告日2005-01-27

    原文格式PDF

  • 申请/专利权人 RAYTHEON COMPANY;

    申请/专利号WO2004US03912

  • 发明设计人 ESSENWANGER KENNETH A.;

    申请日2004-02-10

  • 分类号H03M1/00;G06F1/02;

  • 国家 WO

  • 入库时间 2022-08-21 22:12:39

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