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LOW LATENCY, HIGH CLOCK FREQUENCY PLESIOASYNCHRONOUS PACKET-BASED CROSSBAR SWITCHING CHIP SYSTEM AND METHOD
LOW LATENCY, HIGH CLOCK FREQUENCY PLESIOASYNCHRONOUS PACKET-BASED CROSSBAR SWITCHING CHIP SYSTEM AND METHOD
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机译:基于低延迟,高时钟频率的变电石同步分组交换芯片系统和方法
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摘要
A plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.
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