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DIVERSITY RECEIVER FREE FROM DECODING ERROR, AND CLOCK REGENERATION CIRCUIT FOR DIVERSITY RECEIVER

机译:没有解码错误的多样性接收器,以及多样性接收器的时钟再生电路

摘要

A diversity receiving apparatus separately weights reception signals of a plurality of reception systems using combining coefficients based on a respective amplitude component of each reception signal and combines the weighted reception signals. The diversity receiving apparatus extracts symbol sections in the combined reception signals, and generates a clock for detecting symbols. The diversity receiving apparatus includes a converting unit 314 for uniformly multiplying the combining coefficients if every combining coefficient is below a predetermined threshold and I component ROMs,. Q component ROMs, an I component adder 325 and a Q component adder 326 that combine the reception signals using the multiplied combining coefficients. IMAGE
机译:分集接收设备使用基于每个接收信号的各自幅度分量的组合系数来分别对多个接收系统的接收信号加权,并且对加权后的接收信号进行合并。分集接收设备提取组合的接收信号中的符号部分,并生成用于检测符号的时钟。分集接收设备包括转换单元314和I分量ROM,如果每个组合系数都低于预定阈值,则转换单元314用于均匀地乘以组合系数。 Q分量ROM,I分量加法器325和Q分量加法器326使用相乘的组合系数来组合接收信号。 <图像>

著录项

  • 公开/公告号EP1143676B1

    专利类型

  • 公开/公告日2005-06-01

    原文格式PDF

  • 申请/专利权人 SANYO ELECTRIC CO. LTD.;

    申请/专利号EP19980961585

  • 发明设计人 IINUMA TOSHINORI;

    申请日1998-12-25

  • 分类号H04L27/22;H04B7/08;H04B1/707;

  • 国家 EP

  • 入库时间 2022-08-21 22:10:19

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