SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING LOAD CAPACITANCE OF DEDICATED WRITE BIT LINE DURING READ/SCAN OPERATION AND METHOD FOR THE SAME

摘要

PURPOSE: A semiconductor memory device capable of reducing the load capacitance of a dedicated write bit line during a read/scan operation and a method for the same are provided to reduce power consumption during the read/scan operation. CONSTITUTION: A semiconductor memory device capable of reducing the load capacitance of a dedicated write bit line during a read/scan operation includes a first bit cell array block(310), a second bit cell array block(320), a block dividing logic(330), a write bit line divider(340), a read/write driver(350) and a scan driver(360). The first bit cell array block is provided with a plurality of first bit lines and a plurality of bit cells. The second bit cell array block is provided with a plurality of second bit lines and a plurality of bit cells. The block dividing logic precharges the bit lines or is activated during the write operation. The block dividing logic generates the block dividing signal. The write bit line divider turns on/off the first bit lines and the third bit lines in response to the block dividing control signal. The read/write driver outputs the write data by receiving and processing the input data and outputs the amplified bit cell data during the read operation. And, the scan driver senses and amplifies the read bit cell data during the scan operation to output the amplified bit cell data.