首页> 外国专利> METHOD OF FORMING INTERLAYER DIELECTRIC OF SEMICONDUCTOR DEVICE TO IMPROVE BARRIER CHARACTERISTIC OF PSG LAYER

METHOD OF FORMING INTERLAYER DIELECTRIC OF SEMICONDUCTOR DEVICE TO IMPROVE BARRIER CHARACTERISTIC OF PSG LAYER

机译:形成半导体器件层间介电层以改善PSG层势垒特性的方法

摘要

Purpose: a kind of method for the layer insulation being used to form semiconductor device is arranged to carry out the planarization process for layer insulation, by executing a RTP (rapid thermal treatment), for minimizing a diffusion length of dopant. Construction: a gate electrode (22) for a predetermined shape copies an insulating substrate (21). It is laminated on insulating substrate, including gate electrode for one PSG layers (24). One layer insulation is formed by a BPSG layers (26) are laminated on PSG layers. Layer insulation is planarized by a RTP. RTP includes the first thermal process, is used to shakeout layer insulation and the second thermal process, is used to make a surface of layer insulation hard.
机译:目的:一种用于形成半导体器件的层绝缘的方法被安排为通过执行RTP(快速热处理)来执行用于层绝缘的平坦化工艺,以最小化掺杂剂的扩散长度。构造:预定形状的栅电极(22)复制绝缘基板(21)。将其层压在绝缘基板上,包括一个PSG层的栅极(24)。一层绝缘层是由BPSG层(26)层压在PSG层上形成的。层绝缘通过RTP平面化。 RTP包括第一个热处理,用于去除绝缘层,第二个热处理,用于使绝缘层的表面变硬。

著录项

  • 公开/公告号KR20050003536A

    专利类型

  • 公开/公告日2005-01-12

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030042431

  • 发明设计人 KWAK NOH YEAL;LEE DONG HO;

    申请日2003-06-27

  • 分类号H01L21/31;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:01

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