首页> 外国专利> METHOD FOR FORMING COPPER INTERCONNECTION OF SEMICONDUCTOR DEVICE TO REDUCE RESISTANCE OF COPPER INTERCONNECTION AND IMPROVE INTERVAL OF SIGNAL DELAY TIME

METHOD FOR FORMING COPPER INTERCONNECTION OF SEMICONDUCTOR DEVICE TO REDUCE RESISTANCE OF COPPER INTERCONNECTION AND IMPROVE INTERVAL OF SIGNAL DELAY TIME

机译:形成半导体器件的铜互连以减小铜互连的电阻并改善信号延迟时间的间隔的方法

摘要

Purpose: a kind of method, the copper-connection for being used to form semiconductor device are arranged to reduce the resistance of a copper-connection and improve the interval formation of signal delay time to form copper Diffusion Barrier conductor layer by a MgO layers and a bronze medal-Mg alloy-layers. Construction: the substrate (11) with a damascene pattern is produced. One bronze medal-Mg alloy-layers (14) are formed along the surface of composite structure, including damascene pattern. - Mg layers of copper are heat-treated to ongoing Mg layers and under copper-Mg alloy-layers of form. MgO layer tables on copper-Mg alloy-layers are eliminated. One layers of copper is formed in copper-Mg alloy-layers to be fully filled damascene pattern. Layers of copper, copper-Mg alloy-layers and (14-1) MgO layers lower are polished to one copper-connection of form (150) in damascene pattern.
机译:目的:一种方法是,安排用于形成半导体器件的铜连接以减小铜连接的电阻并改善信号延迟时间的间隔形成,以通过MgO层形成铜扩散阻挡层导体层。铜牌-镁合金层。结构:产生具有镶嵌图案的衬底(11)。沿着包括镶嵌图案的复合结构的表面形成一层铜牌-镁合金层(14)。 -将铜的Mg层热处理为正在进行的Mg层,并在形成的Mg-Cu合金层之下。消除了铜-镁合金层上的MgO层表。在铜-镁合金层中形成一层铜,以完全填充镶嵌图案。铜层,铜-Mg合金层和较低的(14-1)MgO层以镶嵌图案抛光成形式(150)的一个铜连接。

著录项

  • 公开/公告号KR20050009932A

    专利类型

  • 公开/公告日2005-01-26

    原文格式PDF

  • 申请/专利权人 MAGNACHIP SEMICONDUCTOR LTD.;

    申请/专利号KR20030049423

  • 发明设计人 MAENG JONG SUN;

    申请日2003-07-18

  • 分类号H01L21/28;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:56

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