首页> 外国专利> MULTIPROCESSOR SYSTEM INCLUDING SHARED MEMORY UNIT AND PROCESSORS EQUIPPED WITH CACHE MEMORY, AND CACHE-COHERENCY MAINTAINING METHOD THEREOF

MULTIPROCESSOR SYSTEM INCLUDING SHARED MEMORY UNIT AND PROCESSORS EQUIPPED WITH CACHE MEMORY, AND CACHE-COHERENCY MAINTAINING METHOD THEREOF

机译:包括共享存储器单元和配备有缓存存储器的处理器的多处理器系统及其缓存保持方法

摘要

PURPOSE: A multiprocessor system including a shared memory unit and processors equipped with a cache memory, and a cache-coherency maintaining method thereof are provided to maintain the cache-coherency while minimizing design change of the processors not offering a multiprocessor operation environment and reduce power consumption of the system without using a complex logic. CONSTITUTION: The processors(PA-PC) are respectively equipped with at least one cache memory(L1A-L1C,L2A-L2C) and are connected to a bus(110). The memory(140) is shared with at least two processors. A directory memory(130) is arranged to stores sharing information of the cache memories for each data block of the memory. A memory controller(120) is connected between the bus and the directory memory. If a request for accessing the memory is received from one of the processors, the memory controller transfers an interrupt to the sharing processor by referring to the directory memory when the requested data block is shared by other processor.
机译:目的:提供一种包括共享存储单元和配备有高速缓冲存储器的处理器的多处理器系统及其高速缓存一致性保持方法,以维持高速缓存一致性同时最小化不提供多处理器操作环境的处理器的设计变更并降低功耗无需使用复杂逻辑即可消耗系统。组成:处理器(PA-PC)分别配备至少一个高速缓存(L1A-L1C,L2A-L2C),并连接到总线(110)。存储器(140)与至少两个处理器共享。目录存储器(130)被布置为存储用于存储器的每个数据块的高速缓冲存储器的共享信息。存储器控制器(120)连接在总线和目录存储器之间。如果从一个处理器接收到访问存储器的请求,则当所请求的数据块被其他处理器共享时,存储器控制器通过参考目录存储器将中断传送到共享处理器。

著录项

  • 公开/公告号KR20050011152A

    专利类型

  • 公开/公告日2005-01-29

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20030050128

  • 发明设计人 CHUNG SUNG WOO;

    申请日2003-07-22

  • 分类号G06F12/00;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:56

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