CIRCUIT AND METHOD FOR GENERATING MULTI-PHASE CLOCK SIGNALS HAVING HOMOGENEOUS DUTY RATIOS

摘要

PURPOSE: A circuit and a method for generating multi-phase clock signals are provided to improve reliability of the circuit by removing signal delays due to inverter number difference and homogenizing duty ratios of two signals having opposite phases. CONSTITUTION: An input buffer buffers a clock signal to generate a buffered clock signal. A first inverter(INV3) inverts the buffered clock signal. A duty ratio compensation delay circuit removes a delay between the buffered clock signal and the inverted clock signal to minimize the difference of the duty ratio between first and second clock signal. A first combination circuit(12) combines the first compensated clock signal with a phase-delayed in-phase signal to generate a phase-delayed inverted signal. A second combination circuit(14) combines the second compensated clock signal with the inverted signal to generate the phase-delayed in-phase signal. A second inverter(INV8) inverts the phase of the phase-delayed inverted signal to generate the first clock signal. A third inverter(INV13) inverts the phase of the phase-delayed in-phase signal to generate the second clock signal.