PACKET PROCESSOR AND BUFFER MEMORY CONTROLLER FOR EXTRACTING AND ALIGNING PACKET HEADER FIELDS TO IMPROVE EFFICIENCY OF PACKET HEADER PROCESSING OF MAIN PROCESSOR AND METHOD THEREOF

摘要

A packet processor which extracts a packet header field, word-aligns the extracted packet header field, and stores the aligned data in an external memory, for a main processor which processes packets received through a packet communication network. The packet processor includes: a serial-to-parallel converter for converting a packet in a bit stream, which is received via the packet communication network, into a word data, the word data being in a word unit(s) which includes at least one byte; a queue for temporarily storing the converted word data; and a computation part for selecting, among the word data stored in the queue, a word data that corresponds to the packet header, performing bit operations with the selected word data to extract a field therefrom, and expanding the extracted field into word alignment and providing it to the main processor. Computational requirements for the main processor to do bit operations for packet header processing are reduced, and therefore, packet processing efficiency can be improved.