SPL ADDER HAVING HIGH SETTING TIME AND LOW POWER CHARACTERISTIC

摘要

A first inverter (INV1) to S Piel adder of the present invention inverts the input signal (A); The first output signal (/ A) of the first inverter which is input to the source, the conduction control according to the input signal (B) input to gate the output signal of the first inverter (/ A) output from the drain side PMOS transistor (PM1); The input signal (A) is input to the drain, it conducts control according to the input signal (B) input to the gate, and the input signal (A) output from the source side, a first connected in parallel with the PMOS transistor (PM1) a first NMOS transistor (NM1); A second PMOS transistor (PM2) the input signal (A) is input to the source, the conduction control according to the input signal (B) input to the gate to which the input signal (A) output from the drain side; The output signal (/ A) of the first inverter is input to the drain, conducts control according to the input signal (B) input to the gate, and the output signal (/ A) of the first inverter output at the source side, the a second PMOS transistor, the second PMOS transistor, MOS transistor (PM2) and the second en (NM2) connected in parallel with (PM2); A second inverter (INV2) inverting the output signal of said first PMOS transistor (PM1) and the first NMOS transistor (NM1); A third inverter (INV3) inverting the output signal of the second PMOS transistor (PM2) and a second NMOS transistor (NM2); A third PMOS transistor (PM3) is conducting control according to the input signal (C) and the output signal of the second inverter (INV2) to be inputted to the source, input to the gate; And an output signal of the second inverter (INV2) is input to the drain, it conducts control according to the input signal (C) input to the gate a third PMOS transistor (PM3), and outputs an output signal (Y) from the connection point the consists of three PMOS transistor (PM3) and the series-connected third en MOS transistor (NM3).; As described above is the invention yen by forming the conventional S Piel adder consisting of a MOS transistor and a MOS transistor yen PMOS transistor, power consumption is significantly reduced.; The present invention is implemented by the device to the rear end of the PMOS transistor has a faster setting time than conventional S Piel adder.; Accordingly, it is possible to reduce the delay (Delay) and the excessive power consumption, which is problematic in the fine process to the maximum extent.