THE DIVISION METHOD OF LOGICAL FUNCTION FOR DESIGNING IC USING FPGA

摘要

1) it can be a single cell implementation targeted portions of the kernel and the kernel expression of a logical expression that is the segmented object generated by creating all of the kernel comprising a kernel and reverse the kernel of the divided target logic function for dividing the target node, and the kernel It s using a separate divided portion expression also generating all candidates expression containing the candidate division; 2) selecting the best candidate expression based on the type and the number of all the literals candidate expression the generated; 3) FPGA available for the optimal candidate type and the number consists of: dividing the logic function to implement a small number of cell circuits than using, design software (S / W circuit of the FPGA of the MUX structure selected) this logic function division methods for integrated circuit design is described by.